Semiconductor memory and method for driving the same

ABSTRACT

A semiconductor memory includes a storing transistor for storing a data composed of any of an MFS transistor, an MFIS transistor and an MFMIS transistor, and a selecting transistor for selecting the storing transistor. A first well region of a first field effect transistor included in the storing transistor is isolated from a second well region of a second field effect transistor included in the selecting transistor. The semiconductor memory further includes a first voltage supply line for supplying a DC voltage to the first well region of the first field effect transistor, and a second voltage supply line independent of the first voltage supply line for supplying a DC voltage to the second well region of the second field effect transistor.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a nonvolatile semiconductormemory and a method for driving the same. More particularly, it relatesto a semiconductor memory including a storing transistor for storing adata composed of an MFS transistor including a field effect transistorhaving a gate electrode formed on a ferroelectric film, an MFIStransistor including a field effect transistor having a gate electrodeformed on a multi-layer film of a ferroelectric film and a dielectricfilm or an MFMIS transistor including a ferroelectric capacitor formedabove a gate electrode of a field effect transistor, and a method fordriving the same.

[0002] Known one-transistor type nonvolatile semiconductor memorieshaving a ferroelectric film are three types of transistors, that is, anMFS transistor, an MFIS transistor and an MFMIS transistor.

[0003] An MFS transistor has a Metal/Ferroelectric/Semiconductormulti-layer structure and includes a gate insulating film of aferroelectric film directly formed on a channel region of asemiconductor substrate.

[0004] An MFIS transistor has aMetal/Ferroelectric/Insulator/Semiconductor multi-layer structure andincludes a dielectric film serving as a buffer layer formed between agate insulating film of a ferroelectric film and a semiconductorsubstrate. The MFIS transistor is improved in the surface characteristicas compared with the MFS transistor.

[0005] An MFMIS transistor has aMetal/Ferroelectric/Metal/Insulator/Semiconductor multi-layer structureand includes a ferroelectric capacitor formed above a gate electrode ofa field effect transistor having the MOS structure. The MFMIS transistoris formed in either of the following two known structures: In the firststructure, the ferroelectric capacitor is formed above the gateelectrode of the field effect transistor with an insulating filmsandwiched therebetween; and in the second structure, the gate electrodeof the field effect transistor also works as the lower electrode of theferroelectric capacitor.

[0006] In a memory cell using, as a data storing transistor, aone-transistor type nonvolatile semiconductor memory having aferroelectric film (namely, a nonvolatile memory), the memory cell isconstructed by connecting a transistor for gate selection and atransistor for source selection to a data storing transistor of an MFStransistor as disclosed in, for example, Japanese Patent No. 2921812.

[0007]FIG. 14 shows the circuit configuration of the one-transistor typenonvolatile semiconductor memory described in Japanese Patent No.2921812. In FIG. 14, WL denotes a word line for write, RL denotes a wordline for read, GL denotes an operation voltage supply line, BL denotes abit line, Q₁ denotes a data storing transistor, Q₂ denotes a writingtransistor and Q₃ denotes a reading transistor.

[0008] The gate of the data storing transistor Q, is connected to theoperation voltage supply line GL through the writing transistor Q₂, thedrain of the data storing transistor Q₁ is connected to the bit line BLthrough the reading transistor Q₃, and the source of the data storingtransistor Q₁ is grounded. A memory cell array is formed by arranging aplurality of memory cells each having this circuit configuration on asilicon substrate.

[0009] A data erase operation, a data write operation and a data readoperation of the memory cell having this circuit configuration will nowbe described with reference to FIG. 15.

[0010] In the data erase operation, negative potential is applied to awell region of a semiconductor substrate so as to apply a voltagebetween the gate of each data storing transistor Q₁ and the substrate.Thus, the polarization of the ferroelectric film is turned along thesame direction. In this manner, data stored in all the memory cells areerased.

[0011] In the data write operation, a voltage is applied between thesubstrate and the gate of the data storing transistor Q₁ of the memorycell disposed at an address selected by the writing transistor Q₂, so asto reverse the polarization direction of the ferroelectric film of thistransistor (to place it in an on-state) or the polarization direction ofthe ferroelectric film of the transistor is kept (to place it in anoff-state) without applying the voltage between the gate and thesubstrate. Specifically, a data is written by causing either of twokinds of polarized states, that is, to reverse the polarization (whichcorresponds to an on-state) and to keep the polarization (whichcorresponds to an off-state) in accordance with the input data. Sincethe polarized state of the ferroelectric film is kept without applying avoltage, the memory cell functions as a nonvolatile semiconductormemory.

[0012] In the data read operation, the reading transistor Q₃ is turnedon, so as to detect voltage drop accompanied by a current flowing fromthe bit line BL through the channel of the data storing transistor Q₁ toa ground line (namely, a drain-source current). Since the channelresistance is varied depending upon the polarized state of theferroelectric film of the data storing transistor Q₂, a data written inthe data storing transistor Q₁ can be thus read.

[0013] Japanese Laid-Open Patent Publication No. 5-205487 describes anonvolatile semiconductor memory in which a well region of a datastoring transistor of each memory cell is isolated. The circuitconfiguration of this semiconductor memory is basically the same as thatof the aforementioned semiconductor memory, and a well region of a firstfield effect transistor working as a data storing transistor is sharedby a selecting transistor for selecting the storing transistor.

[0014] The aforementioned conventional semiconductor memory has thefollowing problem: A data is written in each storing transistor aftererasing all data stored in the storing transistors sharing the wellregion in a batch by turning the polarization of the ferroelectric filmsalong one direction by applying a voltage to the well region of thefield effect transistors working as the storing transistors, andtherefore, it takes a long time to rewrite (overwrite) data.

[0015] Furthermore, since data stored in a plurality of storingtransistors are erased by applying a voltage to the well region sharedby the plural storing transistors and having large load capacitance, thespeed of a data erase operation is disadvantageously low.

SUMMARY OF THE INVENTION

[0016] In consideration of the aforementioned conventional problems, anobject of the invention is reducing time required for data rewrite(overwrite) by rewriting a data without erasing data having been writtenin storing transistors.

[0017] In order to achieve the object, the semiconductor memory of thisinvention comprises a storing transistor for storing a data composed ofany of an MFS transistor including a first field effect transistorhaving a gate electrode formed on a ferroelectric film, an MFIStransistor including a first field effect transistor having a gateelectrode formed on a multi-layer film of a ferroelectric film and adielectric film and an MFMIS transistor including a ferroelectriccapacitor formed above a gate electrode of a first field effecttransistor, the first field effect transistor having a first wellregion; a selecting transistor for selecting the storing transistorcomposed of a second field effect transistor, the second field effecttransistor having a second well region that is isolated from the firstwell region of the first field effect transistor; a first voltage supplyline for supplying a DC voltage to the first well region of the firstfield effect transistor; and a second voltage supply line independent ofthe first voltage supply line for supplying a DC voltage to the secondwell region of the second field effect transistor.

[0018] In the semiconductor memory of this invention, the first wellregion of the first field effect transistor included in the storingtransistor is isolated from the second well region of the second fieldeffect transistor included in the selecting transistor, and the firstvoltage supply line for supplying the DC voltage to the first wellregion of the first field effect transistor and the second voltagesupply line for supplying the DC voltage to the second well region ofthe second field effect transistor are independently provided.Therefore, while applying a first DC voltage to the first well region ofthe first field effect transistor of the storing transistorindependently of the second well region of the second field effecttransistor of the selecting transistor, a second DC voltage withpolarity positive or negative with respect to the first DC voltageapplied to the first well region can be applied to the control gate ofthe first field effect transistor of the storing transistor, so as towrite a data in the semiconductor memory. Accordingly, withoutconducting an operation for erasing data stored in storing transistors,a data can be written in a desired storing transistor. In other words, adata can be written without conducting the operation for erasing data ofstoring transistors by applying a voltage to a well region shared by theplural transistors and having large load capacitance. As a result, timerequired for data rewrite can be reduced.

[0019] In the semiconductor memory, the second field effect transistorpreferably has higher breakdown voltage than the first field effecttransistor.

[0020] In this case, although the operation speed of the second fieldeffect transistor to which a large voltage is applied is relativelylowered, the breakdown voltage thereof can be increased, and theoperation speed of the first field effect transistor to which a largevoltage is not applied can be increased.

[0021] In the semiconductor memory, it is preferred that the storingtransistor is composed of the MFMIS transistor and that the second fieldeffect transistor includes a gate insulating film having a largerthickness than a gate insulating film of the first field effecttransistor.

[0022] Thus, the second field effect transistor can definitely attainhigher breakdown voltage than the first field effect transistor.

[0023] In the semiconductor memory, it is preferred that the storingtransistor is composed of the MFMIS transistor, that the first fieldeffect transistor and the second field effect transistor have an LDDstructure and that the second field effect transistor includes alightly-doped layer having a larger length than a lightly-doped layer ofthe first field effect transistor.

[0024] Thus, the second field effect transistor can definitely attainhigher breakdown voltage than the first field effect transistor.

[0025] In the semiconductor memory, it is preferred that the storingtransistor is composed of the MFMIS transistor and that the second fieldeffect transistor includes a gate electrode having a larger gate lengththan a gate electrode of the first field effect transistor.

[0026] Thus, the second field effect transistor can definitely attainhigher breakdown voltage than the first field effect transistor.

[0027] In the semiconductor memory, it is preferred that the first fieldeffect transistor, the second field effect transistor and a drivingcircuit for driving the first and second field effect transistors areformed on one semiconductor substrate and that a driving voltagesupplied to the driving circuit and the DC voltage supplied to thesecond well region of the second field effect transistor are suppliedfrom one voltage supply.

[0028] In this case, there is no need to generate the DC voltage to besupplied to the second well region of the second field effecttransistor, and therefore, a DC voltage generation circuit formed on thesemiconductor substrate can be simplified and reduced in its area.

[0029] In the semiconductor memory, the first well region of the firstfield effect transistor and the second well region of the second fieldeffect transistor preferably have, different conductivity types.

[0030] In this manner, the driving voltage supplied to the drivingcircuit and the DC voltage supplied to the second well region of thesecond field effect transistor can be easily supplied from the samevoltage supply. Accordingly, the DC voltage generation circuit formed onthe semiconductor substrate can be definitely simplified.

[0031] The method of this invention for driving a semiconductor memoryincluding a storing transistor for storing a data composed of any of anMFS transistor including a first field effect transistor having a gateelectrode formed on a ferroelectric film, an MFIS transistor including afirst field effect transistor having a gate electrode formed on amulti-layer film of a ferroelectric film and a dielectric film and anMFMIS transistor including a ferroelectric capacitor formed above a gateelectrode of a first field effect transistor, and a selecting transistorfor selecting the storing transistor composed of a second field effecttransistor, the first field effect transistor having a first well regionthat is isolated from a second well region of the second field effecttransistor, comprises a step of writing a data in the storing transistorby applying a first DC voltage to the first well region of the firstfield effect transistor and applying a second DC voltage with polaritypositive or negative with respect to the first DC voltage to a controlgate of the first field effect transistor.

[0032] In the method for driving a semiconductor memory of thisinvention, while applying the first DC voltage to the first well regionof the first field effect transistor included in the storing transistor,the second DC voltage with polarity positive or negative with respect tothe first DC voltage is applied to the control gate of the first fieldeffect transistor, so as to write a data in the semiconductor memory.Therefore, without conducting an operation for erasing data written instoring transistors, a data can be written in a desired storingtransistor. Accordingly, a data can be written without conducting theoperation for erasing data of the storing transistors by applying avoltage to a well region shared by the plural storing transistors andhaving large load capacitance. As a result, the time required for datarewrite can be reduced.

[0033] In the method for driving a semiconductor memory, the secondfield effect transistor preferably has higher breakdown voltage than thefirst field effect transistor.

[0034] In this case, although the operation speed of the second fieldeffect transistor to which a large voltage is applied is relativelylowered, the breakdown voltage thereof can be increased, and theoperation speed of the first field effect transistor to which a largevoltage is not applied can be increased.

[0035] In the method for driving a semiconductor memory, a drivingvoltage supplied to a driving circuit for driving the first and secondfield effect transistors and a DC voltage supplied to the second wellregion of the second field effect transistor are preferably suppliedfrom one voltage supply.

[0036] In this case, since there is no need to generate a DC voltage tobe supplied to the second well region of the second field effecttransistor, a DC voltage generation circuit formed on the semiconductorsubstrate can be simplified and reduced in its area.

[0037] In the method for driving a semiconductor memory, the first wellregion of the first field effect transistor and the second well regionof the second field effect transistor preferably have differentconductivity types.

[0038] Thus, the driving voltage supplied to the driving circuit and theDC voltage supplied to the second well region of the second field effecttransistor can be easily supplied from the same voltage supply.Therefore, the DC voltage generation circuit formed on the semiconductorsubstrate can be definitely simplified.

BRIEF DESCRIPTION OF THE DRAWINGS

[0039]FIG. 1 is a plane view of a memory cell array in which memorycells each including a semiconductor memory according to Embodiment 1are arranged in the form of a matrix;

[0040]FIG. 2 is a diagram of voltages applied in a write operation and aread operation of a memory cell included in the memory cell array inwhich the memory cells each including the semiconductor memory ofEmbodiment 1 are arranged in the form of a matrix;

[0041]FIG. 3 is a diagram of I_(ds)-V_(G) characteristics of an MIStransistor included in an MFMIS transistor and an MFMIS transistor inwhich polarization of a ferroelectric film is reversed by applying avoltage of +8 V or −8 V to its control gate;

[0042]FIG. 4 is a plane view of a semiconductor chip mounting the memorycell array including the memory cells each composed of the semiconductormemory of Embodiment 1;

[0043]FIG. 5 is a cross-sectional view of the semiconductor memory ofEmbodiment 1;

[0044]FIGS. 6A and 6B are cross-sectional views for showing proceduresin fabrication of the semiconductor memory of Embodiment 1

[0045]FIGS. 7A and 7B are cross-sectional views for showing otherprocedures in the fabrication of the semiconductor memory of Embodiment1;

[0046]FIGS. 8A and 8B are cross-sectional views for showing otherprocedures in the fabrication of the semiconductor memory of Embodiment1;

[0047]FIG. 9 is a cross-sectional view for showing another procedure inthe fabrication of the semiconductor memory of Embodiment 1;

[0048]FIG. 10 is a cross-sectional view for showing another procedure inthe fabrication of the semiconductor memory of Embodiment 1;

[0049]FIG. 11 is a plane view of a memory cell array in which memorycells each including a semiconductor memory according to Embodiment 2are arranged in the form of a matrix;

[0050]FIG. 12 is a diagram of voltages applied in a write operation anda read operation of a memory cell included in the memory cell array inwhich the memory cells each including the semiconductor memory ofEmbodiment 2 are arranged in the form of a matrix;

[0051]FIG. 13 is a plane view of a semiconductor chip mounting thememory cell array including the memory cells each composed of thesemiconductor memory of Embodiment 2;

[0052]FIG. 14 is a circuit diagram of a conventional nonvolatilesemiconductor memory; and

[0053]FIG. 15 is a diagram of voltages applied in a write operation anda read operation of the conventional nonvolatile semiconductor memory.

DETAILED DESCRIPTION OF THE INVENTION Embodiment 1

[0054] A semiconductor memory and a method for driving the sameaccording to Embodiment 1 of the invention will now be described withreference to FIGS. 1 through 4. Although the semiconductor memory ofEmbodiment 1 uses an MFMIS transistor as a storing transistor forstoring a data, an MFS transistor or an MFIS transistor may be usedinstead.

[0055]FIG. 1 shows the plane structure of a memory cell array in whichmemory cells each including the semiconductor memory of Embodiment 1 arearranged in the form of a 2×2 matrix. In FIG. 1, WL₁ and WL₂ denote wordlines, SL₁ and SL₂ denote source lines, GL₁ and GL₂ denote operationvoltage supply lines, BL₁ and BL₂ denote bit lines, Q₁₁, Q₁₂, Q₂₁ andQ₂₂ denote field effect transistors for data storage (hereinafter simplyreferred to as storing transistors), C₁₁, C₁₂, C₂₁ and C₂₂ denoteferroelectric capacitors, and P₁₁, P₁₂, P₂₁ and P₂₂ denote field effecttransistors for selecting the storing transistors Q₁₁, Q₁₂, Q₂₁ and Q₂₂(hereinafter simply referred to as selecting transistors). The storingtransistor Q₁₁, Q₁₂, Q₂₁ or Q₂₂ and the ferroelectric capacitor C₁₁,C₁₂, C₂₁ or C₂₂ disposed in the same memory cell together form an MFMIStransistor.

[0056] As shown in FIG. 1, p-type first well regions W₁ and W₂ andp-type second well regions V₇ and V₂ each extending along the columndirection of the memory cell array are alternately provided along therow direction. The storing transistor Q is formed in the first wellregion W, and the selecting transistor P is formed in the second wellregion V.

[0057] The lower electrode of the ferroelectric capacitor C is connectedto the gate electrode (floating gate) of the storing transistor Q, theupper electrode (control gate) of the ferroelectric capacitor C isconnected to the operation voltage supply line GL through the selectingtransistor P, and the gate of the selecting transistor P is connected tothe word line WL. Accordingly, the selecting transistor P is turnedon/off by the word line WL, so as to transfer a signal from theoperation voltage supply line GL to the control gate of the storingtransistor.

[0058] The drain of the storing transistor Q is connected to the bitline BL and the source of the storing transistor Q is connected to thesource line SL, so as to read a data in accordance with a potentialdifference between the bit line BL and the source line SL.

[0059] Now, operations for writing a data in and reading a data from thememory cell disposed at an address 11 (namely, on the first row and inthe first column) of the memory cell array composed of the semiconductormemory of this embodiment will be described with reference to FIG. 2.

Write Operation

[0060] First, as a preparation operation, a DC voltage −V_(p) of, forexample, −8 V is applied to the second well regions V₁ and V₂ where theselecting transistors P are formed (V₁ =V₂=−V_(p)), and the first wellregions W₁ and W₂ where the storing transistors Q are formed aregrounded (W₁=W₂=0 V).

[0061] Thereafter, a data is written in the memory cell at the address11 as follows:

[0062] A voltage +V_(p) is applied to the word line WL₁ on the first rowand a voltage −V_(p) is applied to the word line WL₂ on the second row,thereby turning on the selecting transistors P₁₁ and P₁₂ on the firstrow. Thus, addresses on the first row are selected.

[0063] All the source lines SL₁ and SL₂ are grounded and all the bitlines BL₁ and BL₂ are grounded.

[0064] A voltage +V_(p) or −V_(p) corresponding to a binary data isapplied to the operation voltage supply line GL₁ in the first column,and the operation voltage supply line GL₂ in the second column isgrounded. Thus, the address in the first column is specified.

[0065] In this manner, the address 11 is specified, and the voltage±V_(p) of, for example, ±₈ V is applied between the control gate and thewell of the MFMIS transistor disposed at the address 11, so that thebinary data can be written in the MFMIS transistor disposed at theaddress 11. In this case, since the selecting transistors P₂₁ and P₂₂ onthe second row are off, no data is written in the MFMIS transistorsdisposed on the second row. Also, since the operation voltage supplyline GL₂ in the second column is grounded, the data stored in the MFMIStransistors disposed in the second column are not overwritten.

Read Operation

[0066] A data written in the memory cell at the address 11 is read asfollows:

[0067] A voltage V_(p) is applied to the word line WL₁ on the first rowand a voltage −V_(p) is applied to the word line WL₂ on the second row,so as to turn on the selecting transistors P₁₁and P₁₂ on the first row.Thus, the addresses on the first row are selected.

[0068] A voltage of 0 V is applied to all the source lines SL₁ and SL₂,a voltage V_(d) of, for example, 0.6 V is applied to the bit line EL₁ inthe first column and a voltage of 0 V is applied to the bit line BL₂ inthe second column. Thus, the address in the first column is specified.

[0069] A voltage V_(r) of, for example, 0.7 V is applied to theoperation voltage supply line GL₁ in the first column and a voltage of 0V is applied to the operation voltage supply line GL₂ in the secondcolumn.

[0070] In this manner, the voltage V_(r) is applied to the control gateof the MFMIS transistor disposed at the address 11 and the voltage V_(d)is applied between the drain and the source of the MFMIS transistor.Therefore, a binary data written in the MFMIS transistor disposed at theaddress 11 is detected as a current change appearing between the drainand the source in accordance with the voltage ±V_(p). In this case,since the selecting transistors P₂₁ and P₂₂ on the second row are off,no current flows between the drain and the source of each MFMIStransistor disposed on the second row. Also, since no voltage is appliedbetween the drain and the source of each MFMIS transistor disposed inthe second column, no current flows therethrough.

[0071]FIG. 3 shows the I_(ds)-V_(G) characteristics of an MIS transistorincluded in an MFMIS transistor and an MFMIS transistor in whichpolarization of a ferroelectric film is reversed by applying a voltageof +8 V or −8 V to its control gate. When a data is written by applyinga voltage of, for example, +8 V to the control gate, the threshold valueis shifted toward the minus side, and when a data is written by applyinga voltage of, for example, −8 V to the control gate, the threshold valueis shifted to the plus side. Accordingly, when the voltage V_(r) of 0.7V is applied to the control gate, an I_(ds) ratio, namely, an on/offratio, attained by applying voltages of +8 V and −8 V is larger than1×10³. Therefore, the binary data written in the MFMIS transistor can beread as a current change appearing between the drain and the source asan on/off ratio larger than 1×10³.

[0072]FIG. 4 shows the plane structure of a semiconductor chip 1mounting the memory cell array composed of the semiconductor memory ofEmbodiment 1. On the semiconductor chip 1, the memory cell array 2, arow driver 3, a column driver 4, an I/F circuit 5 and a DC-DC converter6A are formed.

[0073] A power voltage introduced from the outside to a VDD terminal onthe semiconductor chip 1 and a ground voltage introduced from theoutside to a GND terminal on the semiconductor chip 1 are respectivelysupplied to the row driver 3 and the column driver 4 corresponding todriving circuits for driving the memory cell array 2.

[0074] Also, the power voltage introduced to the VDD terminal issupplied to the DC-DC converter 6A, which generates a DC voltage +V_(p), a DC voltage −V₁, a DC voltage V_(d) and a DC voltage V_(r). The DCvoltage +V₁generated by the DC-DC converter 6A is sent to the row driver3 and the column driver 4, the DC voltage −V_(p) generated by the DC-DCconverter 6A is sent to the column driver 4, and the DC voltage V_(d)and the DC voltage V_(r) generated by the DC-DC converter 6A are sent tothe column driver 4.

[0075] In the preparation for a write operation, the DC voltage −V_(p)generated by the DC-DC converter 6A is supplied to the second wellregions V of the memory cell array 2, and the ground voltage introducedto the GND terminal is directly supplied to the first well regions W ofthe memory cell array 2.

[0076] A voltage supply line for supplying the ground voltage introducedto the GND terminal to the first well regions W of the memory cell array2 as the DC voltage of 0 V corresponds to a first voltage supply line,and a voltage supply line for supplying the DC voltage −V_(p) generatedby the DC-DC converter 6A to the second well regions V of the memorycell array 2 as the DC voltage −V_(p) corresponds to a second voltagesupply line.

[0077]FIG. 5 shows the cross-sectional structure of the semiconductormemory of Embodiment 1. An isolation region 11 is formed on asemiconductor substrate 10, and a p-type first well region 12 having arelatively small width and a p-type second well region 13 having arelatively large width are formed in surface portions of thesemiconductor substrate 10 surrounded with the isolation region 11.

[0078] A first gate electrode 16 with a gate length of 0.6 μm is formedabove the first well region 12 with a first gate insulating film 14 witha thickness of 26.5 nm sandwiched therebetween. A second gate electrode17 with a gate length of 1.5 μm is formed above the second well region13 with a second gate insulating film 15 with a thickness of 40 nmsandwiched therebetween. Sidewalls 20 are formed on the respective sidefaces of the first and second gate electrodes 16 and 17.

[0079] N-type first lightly-doped layers 18 with a length of 0.2 μm andn-type heavily-doped layers 22 are formed in surface portions of thefirst well region 12, and n-type second lightly doped layers 19 with alength of 1.5 μm and n-type heavily-doped layers 23 are formed insurface portions of the second well region 13. Also, a first contactlayer 24 of a p-type heavily-doped layer is formed in another surfaceportion of the first well region 12, and a second contact layer 25 of ap-type heavily-doped layer is formed in another surface portion of thesecond well region 13.

[0080] The first lightly-doped layers 18, the first heavily-doped layers22, the first gate insulating film 14 and the first gate electrode 16together form the storing transistor P, and the second lightly-dopedlayers 19, the second heavily-doped layers 23, the second gateinsulating film 15 and the second gate electrode 17 together form theselecting transistor Q. The operation voltage of the storing transistorQ can be set to 5 V and the operation voltage of the selectingtransistor P can be set to 21 V.

[0081] This semiconductor memory has the following threecharacteristics: The second gate insulating film 15 has a largerthickness than the first gate insulating film 14; the second gateelectrode 17 has a larger gate length than the first gate electrode 16;and the second lightly-doped layer 19 has a larger length than the firstlightly-doped layer 18. Owing to at least one of these characteristics,the breakdown voltage of the selecting transistor P is larger than thatof the storing transistor Q.

[0082] A first interlayer insulating film 26 is formed so as to coverthe first and second gate electrodes 16 and 17. A barrier layer 28 of aTiN film, a lower electrode 29 of an Ir film, an IrO₂ film and a Ptfilm, a ferroelectric film 30 of a SrBi₂Ta₂O₉ film with a thickness of200 nm and an upper electrode 31 of a Pt film are formed on the firstinterlayer insulating film 26. The lower electrode 29, the ferroelectricfilm 30 and the upper electrode 31 together form the ferroelectriccapacitor C. The upper electrode 31 of the ferroelectric capacitor C isconnected to the first gate electrode 16 of the storing transistor Qthrough a first contact plug 27.

[0083] A second interlayer insulating film 32 is formed so as to coverthe ferroelectric capacitor C. Lower interconnects 36A, 36B, 36C, 36D,36E, 36F and 36G of an Al film are formed above the second interlayerinsulating film 32 with a barrier layer 35 of a TiN film sandwichedtherebetween. The lower interconnect 36A is connected to the firstcontact layer 24 through a second contact plug 33, the lowerinterconnect 36B is connected to one of the first heavily-doped layers22 through another second contact plug 33, the lower interconnect 36C isconnected to the upper electrode 31 through a third contact plug 34, thelower interconnect 36D is connected to the other of the firstheavily-doped layers 22 through another second contact plug 33, thelower interconnect 36E is connected to one of the second heavily-dopedlayers 23 through another second contact plug 33, the lower interconnect36F is connected to the other of the second heavily-doped layers 23through another second contact plug 33, and the lower interconnect 36Gis connected to the second contact layer 25 through another secondcontact plug 33.

[0084] A third interlayer insulating film 37 is formed so as to coverthe lower interconnects 36A, 36B, 36C, 36D, 36E, 36F and 36G. An upperinterconnect 40 of an Al film is formed above the third interlayerinsulating film 37 with a barrier layer 39 of a TiN film sandwichedtherebetween. The lower interconnect 36D is connected to the upperinterconnect 40 through a fourth contact plug 38.

[0085] A first protection film 41 of a SiO₂ film is formed so as tocover the upper interconnect 40, and a second protection film 42 of aSiN, film is formed on the first protection film 41.

[0086] Now, a method for fabricating the semiconductor memory ofEmbodiment 1 will be described with reference to FIGS. 6A, 6B, 7A, 7B,8A, 8B, 9 and 10.

[0087] First, as shown in FIG. 6A, an isolation region 11 of SiO₂ isformed on a semiconductor substrate 10 of Si by the LOCOS method. Ap-type dopant is ion implanted into surface portions of thesemiconductor substrate 10 surrounded with the isolation region 11,thereby forming a p-type first well region 12 having a relatively smallwidth and a p-type second well region 13 having a relatively largewidth.

[0088] Next, the semiconductor substrate 10 is subjected to thermaloxidation, so as to form a SiO₂ film with a thickness of 26.5 nm on thefirst and second well regions 12 and 13. A portion of the SiO₂ filmformed on the first well region 12 is selectively removed by etching.Thus, a second gate insulating film 15 is formed from the SiO₂ film witha thickness of 26.5 nm on the second well region 13 as shown in FIG. 6B.

[0089] Then, the semiconductor substrate 10 is subjected to the thermaloxidation again, so as to form a first gate insulating film 14 of a SiO₂film with a thickness of 13.5 nm on the first well region 12 andincrease the thickness of the second gate insulating film 15 formed onthe second well region 12 to 40 nm as shown in FIG. 7A.

[0090] Next, after depositing a polysilicon film with a thickness of 300nm on the first and second gate insulating films 14 and 15, thepolysilicon film is doped with phosphorus ions, and the polysilicon filmdoped with phosphorus is patterned. Thus, a first gate electrode 16 witha gate length of 0.6 μm is formed on the first insulating film 14 and asecond gate electrode 17 with a gate length of 1.5 μm is formed on thesecond insulating film 15 as shown in FIG. 7B. Thereafter, n-type dopantions are implanted into surface portions of the first well region 12with the first gate electrode 16 used as a mask, thereby forming n-typefirst lightly-doped layers 18, and n-type dopant ions are implanted intosurface portions of the second well region 13 with the second gateelectrode 17 used as a mask, thereby forming n-type second lightly-dopedlayers 19.

[0091] Next, after depositing a SiO₂ film over the semiconductorsubstrate 10, the SiO₂ film is anisotropically etched, so as to formsidewalls 20 on the side faces of the first and second gate electrodes16 and 17 as shown in FIG. 8A. Then, after a resist pattern 21 havingopenings in regions for forming heavily-doped layers is formed on thesemiconductor substrate 10, n-type dopant ions are doped by using theresist pattern 21 as a mask. Thus, first heavily-doped layers 22 areformed in the first well region 12 and second heavily-doped layers 23are formed in the second well region 13. In this case, since the resistpattern 21 covers the second gate electrode 17 but does not cover thefirst gate electrode 16, the length (1.5 μm) of a portion of the secondlightly-doped layer 19 closer to the second gate electrode is largerthan the length (0.2 μm) of a portion of the first lightly-doped layer18 closer to the first gate electrode.

[0092] In this manner, a storing transistor Q including the firstlightly-doped layers 18, the first heavily-doped layers 22, the firstgate insulating film 14 and the first gate electrode 16 is formed, and aselecting transistor P including the second lightly-doped layers 19, thesecond heavily-doped layers 23, the second gate insulating film 15 andthe second gate electrode 17 is formed.

[0093] Next, although not shown in the drawings, a resist pattern havingopenings in regions for forming contact layers is formed on thesemiconductor substrate 10, and p-type dopant ions are doped by usingthe resist pattern as a mask. Thus, as shown in FIG. 8B, a first contactlayer 24 is formed in the first well region 12 and a second contactlayer 25 is formed in the second well region 13. Subsequently, annealingis carried out at a temperature of 900° C., and a first interlayerinsulating film 26 of a SiO₂ film is formed over the semiconductorsubstrate 10.

[0094] Then, as shown in FIG. 9, a plug hole is formed in the firstinterlayer insulating film 26, and a polysilicon film is deposited onthe first interlayer insulating film 26. Thereafter, a portion of thepolysilicon film deposited outside of the plug hole is removed, so as toform, in the first interlayer insulating film 26, a first contact plug27 for connection to the second gate electrode 17.

[0095] Next, a multi-layer film is formed by successively depositing aTiN film, an Ir film, an IrO₂ film and a Pt film on the first interlayerinsulating film 26 by sputtering, and the multi-layer film is patterned,thereby forming a barrier layer 28 of the TiN film and a lower electrode29 of the Ir film, the IrO₂ film and the Pt film. Then, a firstSrBi₂Ta₂O₉ film (hereinafter referred to as an SBT film) with athickness of 100 nm is formed on the lower electrode 29 by spin coating,and the first SBT film is crystallized by carrying out annealing at 800°C. Thereafter, a second SBT film with a thickness of 100 nm is formed onthe first SBT film by the spin coating, and the second SBT film iscrystallized by carrying out annealing at 800° C. Next, a Pt film isdeposited on the second SBT film by the sputtering, and the Pt film, thesecond SBT film and the first SBT film are patterned, thereby forming aferroelectric film 30 of the first and second SBT films and an upperelectrode 31 of the Pt film.

[0096] In this manner, a ferroelectric capacitor C including the lowerelectrode 29, the ferroelectric film 30 and the upper electrode 31 isformed, and the first gate electrode 16 of the storing transistor Q isconnected to the upper electrode 31 of the ferroelectric capacitor Cthrough the first contact plug 27.

[0097] Next, as shown in FIG. 10, a second interlayer insulating film 32of a SiO₂ film is deposited so as to cover the ferroelectric capacitorC, and the second interlayer insulating film 32 is planarized by CMP.Then, via holes are formed in the second interlayer insulating film 32and a W film is deposited over the second interlayer insulating film 32.A portion of the W film exposed on the second interlayer insulating film32 is removed, so as to form, in the first interlayer insulating film 26and the second interlayer insulating film 32, second contact plugs 33from the W film and to form a third contact plug 34 in the secondinterlayer insulating film 32.

[0098] Then, a TiN film and an Al film are successively deposited on thesecond interlayer insulating film 32, and the TiN film and the Al filmare patterned, thereby forming a barrier layer 35 of the TiN film andlower interconnects 36A, 36B, 36C, 36D, 36E, 36F and 36G of the A1 film.In this case, the lower interconnect 36A is connected to the firstcontact layer 24 through the second contact plug 33, the lowerinterconnect 36B is connected to one of the first heavily-doped layers22 through the second contact plug 33, the lower interconnect 36C isconnected to the upper electrode 31 through the third contact plug 34,the lower interconnect 36D is connected to the other of the firstheavily-doped layers 22 through the second contact plug 33, the lowerinterconnect 36E is connected to one of the second heavily-doped layers23 through the second contact plug 33, the lower interconnect 36F isconnected to the other of the second heavily-doped layers 23 through thesecond contact plug 33, and the lower interconnect 36G is connected tothe second contact layer 25 through the second contact plug 33.

[0099] Next, a third interlayer insulating film 37 of a SiO₂ film isdeposited so as to cover the lower interconnects 36A, 36B, 36C, 36D,36E, 36F and 36G, and the third interlayer insulating film 37 isplanarized by the CMP. Thereafter, a fourth contact plug 38 is formed inthe third interlayer insulating film 37 similarly to the second andthird contact plugs 33 and 34.

[0100] Subsequently, a TiN film and an Al film are successivelydeposited on the third interlayer insulating film 32, and the TiN filmand the Al film are patterned, thereby forming a barrier layer 39 of theTiN film and an upper interconnect 40 of the Al film. In this case, thelower interconnect 36D is connected to the upper interconnect 40 throughthe fourth contact plug 38.

[0101] Next, a first protection film 41 of SiO₂ film is deposited so asto cover the upper interconnect 40 and a second protection film 42 of aSiN. film is deposited on the first protection film 41. Thus, thesemiconductor memory of Embodiment 1 shown in FIG. 5 is completed.

Embodiment 2

[0102] A semiconductor memory and a method for driving the sameaccording to Embodiment 2 of the invention will now be described withreference to FIGS. 11 through 13. Although the semiconductor memory ofEmbodiment 2 uses an MFMIS transistor as a storing transistor forstoring a data, an MFS transistor or an MFIS transistor may be usedinstead.

[0103]FIG. 11 shows the plane structure of a memory cell array in whichmemory cells each including the semiconductor memory of Embodiment 2 arearranged in the form of a 2×2 matrix. In FIG. 11, WL₁ and WL₂ denoteword lines, SL₁ and SL₂ denote source lines, GL₁ and GL₂ denoteoperation voltage supply lines, BL₁ and BL₂ denote bit lines, Q₁₁, Q₁₂,Q₂₁ and Q₂₂ denote storing transistors, C₁₁, C₁₂, C₂₁ and C₂₂ denoteferroelectric capacitors, and P₁₁, P₁₂, P₂, and P₂₂ denote selectingtransistors. The storing transistor Q₁₁, Q₁₂, Q₂₁ or Q₂₂ and theferroelectric capacitor C₁₁, C₁₂, C₂₁ or C₂₂ disposed in the same memorycell together form an MFMIS transistor.

[0104] N-type first well regions W₁ and W₂ and p-type second wellregions V₁ and V₂ each extending along the column direction of thememory cell array are alternately provided along the row direction. Thestoring transistor Q is formed in the first well region W, and theselecting transistor P is formed in the second well region V.

[0105] In the same manner as in Embodiment 1, the lower electrode of theferroelectric capacitor C is connected to the gate electrode (floatinggate) of the storing transistor Q, the upper electrode (control gate) ofthe ferroelectric capacitor C is connected to the operation voltagesupply line GL through the selecting transistor P, and the gate of theselecting transistor P is connected to the word line WL.

[0106] The drain of the storing transistor Q is connected to the bitline BL and the source of the storing transistor Q is connected to thesource line SL, so as to read a data in accordance with a potentialdifference between the bit line BL and the source line SL.

[0107] Now, operations for writing a data in and reading a data from thememory cell disposed at an address 11 (namely, on the first row and inthe first column) of the memory cell array composed of the semiconductormemory of this embodiment will be described with reference to FIG. 12.

Write Operation

[0108] First, as a preparation operation, a DC voltage V_(p)of, forexample, +8 V is applied to the second well regions V where theselecting transistors P are formed (V₁=V₂=V_(p)), and the first wellregions W where the storing transistors Q are formed are grounded(W₁=W₂=0 V).

[0109] Thereafter, a data is written in the memory cell at the address11 as follows:

[0110] A voltage −V_(p) is applied to the word line WL₁ on the first rowand the word line WL₂ on the second row is grounded, thereby turning onthe selecting transistors P₁₁ and P₁₂ disposed on the first row. Thus,addresses on the first row are selected.

[0111] All the source lines SL₁ and SL₂ are grounded and all the bitlines BL₁ and BL₂ are grounded.

[0112] A voltage +V_(p) or −V_(p) corresponding to a binary data isapplied to the operation voltage supply line GL₁ in the first column,and the operation voltage supply line GL₂ in the second column isgrounded. Thus, the address in the first column is specified.

[0113] In this manner, the address 11 is specified, and a voltage ±V_(p)of, for example, ±8 V is applied between the control gate and the wellof the MFMIS transistor disposed at the address 11, so that the binarydata can be written in the MFMIS transistor at the address 11. In thiscase, since the selecting transistors P₂₁ and P₂₂ disposed on the secondrow are off, no data is written in the MFMIS transistors on the secondrow. Also, since the operation voltage supply line GL₂ in the secondcolumn is grounded, the data stored in the MFMIS transistors in thesecond column are not overwritten.

Read Operation

[0114] A data written in the memory cell at the address 11 is read asfollows:

[0115] A voltage −V_(p) is applied to the word line WL₁ on the first rowand a voltage of 0 V is applied to the word line WL2 on the second row,so as to turn on the selecting transistors P₁₁and P₁₂ on the first row.Thus, the addresses on the first row are selected.

[0116] A voltage of 0 V is applied to all the source lines SL₁ and SL₂,a voltage V_(d) of, for example, 0.6 V is applied to the bit line BL₁ inthe first column and a voltage of 0 V is applied to the bit line BL₂ inthe second column. Thus, the address in the first column is specified.

[0117] A voltage V_(r) of, for example, 0.7 V is applied to theoperation voltage supply line GL₁ in the first column and a voltage of 0V is applied to the operation voltage supply line GL₂ in the secondcolumn.

[0118] In this manner, the voltage V_(r) is applied to the control gateof the MFMIS transistor disposed at the address 11 and the voltage V_(d)is applied between the drain and the source of the MFMIS transistor.Therefore, a binary data written in the MFMIS transistor disposed at theaddress 11 is detected as a current change appearing between the drainand the source in accordance with the voltage ±V_(p). In this case,since the selecting transistors P₂₁ and P₂₂ disposed on the second roware off, no current flows between the drain and the source of each MFMIStransistor disposed on the second row. Also, since no voltage is appliedbetween the drain and the source of each MFMIS transistor disposed inthe second column, no current flows therethrough.

[0119]FIG. 13 shows the plane structure of a semiconductor chip 1mounting the memory cell array composed of the semiconductor memory ofEmbodiment 2. On the semiconductor chip 1, the memory cell array 2, arow driver 3, a column driver 4, an I/F circuit 5 and a DC-DC converter6B are formed.

[0120] A power voltage introduced from the outside to a VDD terminal onthe semiconductor chip 1 and a ground voltage introduced from theoutside to a GND terminal on the semiconductor chip 1 are respectivelysupplied to the row driver 3 and the column driver 4 corresponding todriving circuits for driving the memory cell array 2.

[0121] Also, the power voltage introduced to the VDD terminal issupplied to the DC-DC converter 6B, which generates a DC voltage −V_(p),a DC voltage V_(d) and a DC voltage V_(r). The DC voltage −V_(p)generated by the DC-DC converter 6B is sent to the row driver 3 and thecolumn driver 4, and the DC voltage V_(d) and the DC voltage V_(r)generated by the DC-DC converter 6B are sent to the column driver 4.

[0122] In the preparation for a write operation, the power voltage V_(p)introduced to the VDD terminal is directly supplied to the second wellregions V of the memory cell array 2, and the ground voltage introducedto the GND terminal is directly supplied to the first well regions w ofthe memory cell array 2.

[0123] A voltage supply line for supplying the ground voltage introducedto the GND terminal to the first well regions W of the memory cell array2 corresponds to a first voltage supply line, and a voltage supply linefor supplying the power voltage introduced to the VDD terminal to thesecond well regions V of the memory cell array 2 corresponds to a secondvoltage supply line.

[0124] In Embodiment 2, since the power voltage introduced to the VDDterminal is directly supplied to the second well regions V of the memorycell array 2 as the DC voltage V_(p), the DC-DC converter 6B need notgenerate a DC voltage +V_(p). Therefore, the area of the DC-DC converter6B of Embodiment 2 can be smaller than that of the DC-DC converter 6A ofEmbodiment 1.

What is claimed is:
 1. A semiconductor memory comprising: a storingtransistor for storing a data composed of any of an MFS transistorincluding a first field effect transistor having a gate electrode formedon a ferroelectric film, an MFIS transistor including a first fieldeffect transistor having a gate electrode formed on a multi-layer filmof a ferroelectric film and a dielectric film and an MFMIS transistorincluding a ferroelectric capacitor formed above a gate electrode of afirst field effect transistor, said first field effect transistor havinga first well region; a selecting transistor for selecting said storingtransistor composed of a second field effect transistor, said secondfield effect transistor having a second well region that is isolatedfrom said first well region of said first field effect transistor; afirst voltage supply line for supplying a DC voltage to said first wellregion of said first field effect transistor; and a second voltagesupply line independent of said first voltage supply line for supplyinga DC voltage to said second well region of said second field effecttransistor.
 2. The semiconductor memory of claim 1, wherein said secondfield effect transistor has higher breakdown voltage than said firstfield effect transistor.
 3. The semiconductor memory of claim 2, whereinsaid storing transistor is composed of said MFMIS transistor, and saidsecond field effect transistor includes a gate insulating film having alarger thickness than a gate insulating film of said first field effecttransistor.
 4. The semiconductor memory of claim 2, wherein said storingtransistor is composed of said MFMIS transistor, said first field effecttransistor and said second field effect transistor have an LDDstructure, and said second field effect transistor includes alightly-doped layer having a larger length than a lightly-doped layer ofsaid first field effect transistor.
 5. The semiconductor memory of claim2, wherein said storing transistor is composed of said MFMIS transistor,and said second field effect transistor includes a gate electrode havinga larger gate length than a gate electrode of said first field effecttransistor.
 6. The semiconductor memory of claim 1, wherein said firstfield effect transistor, said second field effect transistor and adriving circuit for driving said first and second field effecttransistors are formed on one semiconductor substrate, and a drivingvoltage supplied to said driving circuit and the DC voltage supplied tosaid second well region of said second field effect transistor aresupplied from one voltage supply.
 7. The semiconductor memory of claim1, wherein said first well region of said first field effect transistorand said second well region of said second field effect transistor havedifferent conductivity types.
 8. A method for driving a semiconductormemory including a storing transistor for storing a data composed of anyof an MFS transistor including a first field effect transistor having agate electrode formed on a ferroelectric film, an MFIS transistorincluding a first field effect transistor having a gate electrode formedon a multi-layer film of a ferroelectric film and a dielectric film andan MFMIS transistor including a ferroelectric capacitor formed above agate electrode of a first field effect transistor, and a selectingtransistor for selecting said storing transistor composed of a secondfield effect transistor, said first field effect transistor having afirst well region that is isolated from a second well region of saidsecond field effect transistor, comprising: a step of writing a data insaid storing transistor by applying a first DC voltage to said firstwell region of said first field effect transistor and applying a secondDC voltage with polarity positive or negative with respect to said firstDC voltage to a control gate of said first field effect transistor. 9.The method for driving a semiconductor memory of claim 8, wherein saidsecond field effect transistor has higher breakdown voltage than saidfirst field effect transistor.
 10. The method for driving asemiconductor memory of claim 8, wherein a driving voltage supplied to adriving circuit for driving said first and second field effecttransistors and a DC voltage supplied to said second well region of saidsecond field effect transistor are supplied from one voltage supply. 11.The method for driving a semiconductor memory of claim 8, wherein saidfirst well region of said first field effect transistor and said secondwell region of said second field effect transistor have differentconductivity types.